The present invention is directed to integrated circuits and, more particularly, to alert signaling from a slave device in an inter-integrated circuit (I2C) bus system.
The I2C (also known as I2C and IIC) bus system is a de facto standard described in “I2C-bus specification and user manual” UM10404 of NXP Semiconductors B.V. The I2C bus system is a bidirectional two-line bus for efficient communication and control between master and slave integrated circuit (IC) devices (or nodes) coupled by the bus. A master is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device addressed is considered a slave.
The two-line I2C bus has a serial data (SDA) line and a serial clock (SCL) line. Both the SDA and SCL lines are bidirectional lines, connected to a voltage supply, such as VDD, through a current source or a pull-up resistor. The high voltage of the I2C bus standard is described as positive, but it will be appreciated that the polarity of the voltages could be inverted. Pulling the line low is normally considered a logical zero (de-assert) while letting the line float high is a logical one (assert). Multiple nodes may be driving the lines simultaneously. If any node is driving the line low, the line will be at low voltage. Nodes that are trying to transmit a logical one by letting the line float high can detect that another node is active at the same time by the fact that the line voltage is pulled low.
Data is transmitted in I2C frames on the SDA line in 8-bit bytes, with each byte followed by an Acknowledge (ACK) bit or a Not Acknowledge (NACK) bit, and clocking information is transmitted on the SCL line. While the SCL line is low, the transmitter (initially the master device) can set the SDA line to the voltage corresponding to the bit to be transmitted and then must wait until sufficiently long after the SCL line has actually gone high for the receiver to register the signal.
Slave devices may hold the SCL line low, giving slave devices a flow control mechanism called clock stretching. If a master transmitter does not have the optional clock stretching function, it will send data without waiting for the SCL line to be high in fact, and the data signal can be lost or crushed. I2C also can be used to wake up a slave microcontroller unit (MCU) device from low power mode (sleep). However, the power management controller (PMC) and clock of the slave MCU take time to wake up. The I2C bus can be held during the wake up delay, by waiting long enough to cover the worst case, by slowing the clock and data frequencies, or by performing repeat starts until receiving a correct ACK signal. However, such actions deteriorate latency and reduce transfer speed.
In the related System Management Bus (SMBus) system, the bus has a third line that can be used for a slave device to send an alert signal to the master device. The alert signal can be a ready signal from an addressed slave device, or can signal a claim to priority when the master device is communicating with other slave devices. This procedure requires the third line and the protocol is slow, since the master device sends a message to the general address of all slave devices in the system, after which the slave device that initiated the alert sends its address.
It would be advantageous to have an I2C bus system where alert signals can be sent from a slave device to a master device that does not systematically deteriorate the latency or speed of the system and that does not require a third bus line nor use of a General-Purpose Input/Output (GPIO) pin.